1. Technical Field
The present invention generally relates to changing logical networks to aid in implementing change orders and in particular to changing logical networks that have been optimized from a hardware description language.
2. Description of the Related Art
There are times when an existing random logic macro (RLM) netlist needs to be modified to implement an engineering change order (ECO) to fix a problem or add an enhancement without changing and/or affecting other sections of the netlist. For example, to implement an ECO in a RLM, a circuit designer must be able to identify nets in a logical cone affected by the ECO and nets with which the circuit designer can construct new logic specified by the ECO. When logical optimization happens, nets that exist in a hardware description language (e.g., VHDL (VHSIC (Very-High Speed Integrated Circuits) Hardware Description Language), Verilog, etc.) may not exist in an optimized netlist. This happens because one or more computer-implemented optimization methods have been applied such that, in creating the optimized netlist, one or more simple functions may have been combined into complex functions and/or one or more complex functions may have been expanded into simple functions.